1. Field of the Invention
The present invention generally relates to a thin film magnetic memory device. More particularly, the present invention relates to a random access memory (RAM) including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device capable of non-volatile data storage using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and also capable of random access to each thin film magnetic element.
In particular, recent announcement shows that the use of tunneling magneto-resistance elements (i.e., thin film magnetic elements having a magnetic tunnel junction (MTJ)) in memory cells significantly improves performance of the MRAM device. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000, and “A 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 44 schematically shows the structure of a memory cell having a magnetic tunnel junction (hereinafter, sometimes simply referred to as “MTJ memory cell”).
Referring to FIG. 44, the MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance varying according to the storage data level, and an access element ATR for forming a path of a sense current Is flowing through tunneling magneto-resistance element TMR in data read operation. Since a field effect transistor is typically used as access transistor ATR, access element ATR is hereinafter sometimes referred to as access transistor ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR.
A digit line DL for data write operation, a word line WL for data read operation, and a bit line BL are provided for the MTJ memory cell. Bit line BL is a data line for transmitting an electric signal corresponding to the storage data level in data read and write operations.
FIG. 45 is a conceptual diagram illustrating data read operation from the MTJ memory cell.
Referring to FIG. 45, tunneling magneto-resistance element TMR has a ferromagnetic material layer FL having a fixed magnetization direction (hereinafter, sometimes simply referred to as “fixed magnetic layer”), and a ferromagnetic material layer VL that is magnetized in the direction according to an external magnetic field (hereinafter, sometimes simply referred to as “free magnetic layer”). A tunneling barrier (tunneling film) TB of an insulator film is interposed between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized either in the same (parallel) direction as, or in the opposite (antiparallel) direction to, that of fixed magnetic layer FL according to the write data level. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
In data read operation, access transistor ATR is turned ON in response to activation of word line WL, and tunneling magneto-resistance element TMR is connected between bit line BL and ground voltage GND. As a result, a bias voltage according to a bit line voltage is applied across tunneling magneto-resistance element TMR, and a tunneling current is supplied to the tunneling film. The use of such a tunneling current enables a sense current to be supplied to a current path formed by bit line BL, tunneling magneto-resistance element TMR, access transistor ATR and ground voltage GND in data read operation.
The electric resistance of tunneling magneto-resistance element TMR varies according to the relation of the magnetization direction between fixed magnetic layer FL and free magnetic layer VL. More specifically, tunneling magneto-resistance element TMR has a minimum electric resistance value Rmin when fixed magnetic layer FL and free magnetic layer VL have parallel magnetization directions, and has a maximum electric resistance value Rmax when they have opposite (antiparallel) magnetization directions.
Accordingly, provided that free magnetic layer VL is magnetized in the direction according to the storage data level, a voltage change caused by sense current Is at tunneling magneto-resistance element TMR varies depending on the storage data level. For example, by supplying sense current Is to tunneling magneto-resistance element TMR after precharging bit line BL to a prescribed voltage, the storage data in the MTJ memory cell can be read by sensing a voltage on bit line BL.
FIG. 46 is a conceptual diagram illustrating data write operation to the MTJ memory cell.
Referring to FIG. 46, in data write operation, word line WL is inactivated and access transistor ATR is turned OFF. In this state, a data write current is applied to digit line DL and bit line BL in order to magnetize free magnetic layer VL in the direction according to the write data.
FIG. 47 is a conceptual diagram illustrating the relation between the data write current and the magnetization direction of the tunneling magneto-resistance element in data write operation.
Referring to FIG. 47, the abscissa H(EA) indicates a magnetic field that is applied to free magnetic layer VL of tunneling magneto-resistance element TMR in the easy-axis (EA) direction. The ordinate H(HA) indicates a magnetic field that is applied to free magnetic layer VL in the hard-axis (HA) direction. Magnetic field H(EA) corresponds to one of two magnetic fields produced by the currents flowing through bit line BL and digit line DL, and magnetic field H(HA) corresponds to the other magnetic field.
In the MTJ memory cell, fixed magnetic layer FL is magnetized in the fixed direction along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized either in the direction parallel or antiparallel (opposite) to that of fixed magnetic layer FL along the easy axis according to the storage data level (“1” and “0”). The MTJ memory cell is thus capable of storing 1-bit data (“1” and “0”) by using the two magnetization directions of free magnetic layer VL.
The magnetization direction of free magnetic layer VL is rewritable only when the sum of the applied magnetic fields H(EA), H(HA) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetization direction of free magnetic layer VL will not change if an applied data write magnetic field corresponds to the region inside the asteroid characteristic line.
As shown by the asteroid characteristic line, applying a magnetic field of the hard-axis direction to free magnetic layer VL enables reduction in a magnetization threshold value required to change the magnetization direction along the easy axis.
When the operation point of the data write operation is designed as in the example of FIG. 47, a data write magnetic field of the easy-axis direction is designed to have strength HWR in the MTJ memory cell to be written. In other words, the data write current to be applied to bit line BL or digit line DL is designed to produce such a data write magnetic field HWR. In general, data write magnetic field HWR is defined by the sum of a switching magnetic field HSW required to switch the magnetization direction and a margin ΔH. Data write magnetic field HWR is thus defined by HWR=HSW+ΔH.
In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of tunneling magneto-resistance element TMR, a data write current of at least a prescribed level must be applied to both digit line DL and bit line BL. Free magnetic layer VL in tunneling magneto-resistance element TMR is thus magnetized in the direction parallel or opposite (antiparallel) to that of fixed magnetic layer FL according to the direction of the data write magnetic field along the easy axis (EA). The magnetization direction written to tunneling magneto-resistance element TMR, i.e., the storage data of the MTJ memory cell, is held in a non-volatile manner until another data write operation is conducted.
The electric resistance of tunneling magneto-resistance element TMR thus varies according to the magnetization direction that is rewritable by an applied data write magnetic field. Therefore, non-volatile data storage can be conducted by correlating electric resistance values Rmax, Rmin of tunneling magneto-resistance element TMR with the storage data levels (“1” and “0”).
FIG. 48 shows the overall structure of an MRAM device 10 integrating MTJ memory cells MC arranged in a matrix.
Referring to FIG. 48, MRAM device 10 has N memory blocks MB0 to MBn−1 (where n is a natural number). Hereinafter, memory blocks MB0 to MBn−1 are sometimes generally referred to as memory blocks MB.
Each memory block MB includes word lines WL and digit lines DL provided corresponding to memory cell rows, and bit lines BL provided corresponding to memory cell columns.
In the case of a large-capacity memory array, a memory array including MTJ memory cells MC arranged in a matrix is commonly divided into a plurality of memory blocks according to functions and applications.
In the case where a memory array is divided into a plurality of memory blocks, a DL/WL driver band for driving a digit line and the like must be provided for each memory block MB. Moreover, a row decoder 110 must be provided for each DL/WL driver band in order to control the respective DL/WL driver band.
FIG. 49 is a conceptual diagram of row selection circuitry having a row decoder 110 for each DL/WL driver band.
Memory blocks MB0, MB1 will be exemplarily described herein. Since the other memory blocks MB2 to MBn−1 have the same structure as that of memory blocks MB0, MB1, description thereof will not be repeated.
Referring to FIG. 49, DL/WL driver bands DWG0, DWG1 corresponding to memory blocks MB0, MB1 respectively include digit line drivers DLD0, DLD1 for controlling supply of a data write current to each digit line DL. Row decoder 110 is provided for each memory block MB.
Row decoder 110 outputs a signal indicating the row selection result based on a row address RA and a write enable WE. A digit line DL in memory block MB0 is selectively activated in response to the output signal of a corresponding row decoder 110 and a block selection signal DLBS0. Block selection signal DLBS0 is a signal for selecting memory block MB0. Similarly, a digit line DL in memory block MB1 is selectively activated in response to the output signal of a corresponding row decoder 110 and a block selection signal DLBS1.
In the above structure, row decoder 110 must be provided for each DL/WL driver band. Therefore, the above structure requires the area for the row decoders, thereby increasing the overall area of the MRAM device.
As described above, data write operation from MTJ memory cell MC is conducted according to two magnetic fields generated by currents flowing through bit line BL and digit line DL. In other words, in order to write data to a selected memory cell, a current is supplied to a selected digit line DL and a selected bit line BL. In this case, a leak magnetic field is applied to a digit line adjacent to selected digit line DL. Theoretically, a magnetic field corresponding to the region inside the asteroid characteristic line in FIG. 47 is applied to an adjacent memory cell corresponding to the adjacent digit line and selected bit line BL. Therefore, a normal memory cell having strong disturb characteristics is not subjected to erroneous writing, but a memory cell having weak disturb characteristics may possibly be subjected to erroneous writing. It is therefore necessary to remove defective memory cells having weak disturb characteristics in advance.
In order to remove such defective memory cells, the memory cells must be tested by supplying a current to the digit lines one by one. Hereinafter, such an operation test for evaluating anti-erroneous writing is referred to as “disturb test”. It takes a long time to conduct the disturb test.
As described above, digit lines DL are provided corresponding to the memory cell rows. However, the line pitch of digit lines DL is approximately the same as the layout pitch of the memory cells. With reduction in memory cell size, the line pitch of digit lines DL is reduced. This causes reduction in manufacturing yield and reliability due to the defects between digit lines DL. Accordingly, a burn-in test of digit lines DL is required. However, since digit lines DL are current lines, a sufficient voltage difference cannot be provided between each of digit lines DL and between digit lines DL and signal lines and between digit lines DL and contacts of other wiring layers and the like. As a result, the burn-in test cannot be conducted in a satisfactory manner even if a voltage for driving a digit line is boosted.